A novel topology for a HEMT negative current mirror

A new solution for the implementation of a HEMT negative current source is presented. The topology can be also profitably employed as a current mirror and as an active load in high-gain MMICs voltage amplifiers. A small-signal model of the proposed circuit is developed which allows to find accurate expressions for the required transfer functions (i.e., the output impedance of the current source, and the current gain of the circuit when operated as a current mirror). Design examples using Philips PML ED02AH GaAs PHEMT process are provided. Spice simulations show that a 10- kW output impedance for the current source and a 35dB voltage gain for a differential pair loaded with the proposed current mirror are easily achieved

Design of low-voltage power efficient frequency dividers in folded MOS current mode logic

In this paper we propose a methodology to design high-speed, power-efficient static frequency dividers based on the low-voltage Folded MOS Current Mode Logic (FMCML) approach. A modeling strategy to analyze the dependence of propagation delay and power consumption on the bias currents of the divide-by-2 (DIV2) cell is introduced. We demonstrate that the behavior of the FMCML DIV2 cell is different both from the one of the conventional MCML DFF (D-type Flip-Flop) and from FMCML DFF without a level shifter. Then an analytical strategy to optimize the divider in different design scenarios: maximum speed, minimum power-delay product (PDP) or minimum energy-delay product (EDP) is presented. The possibility to scale the bias currents through the divider stages without affecting the speed performance is also investigated. The proposed analytical approach allows to gain a deep insight into the circuit behavior and to comprehensively optimize the different design tradeoffs. The derived models and design guidelines are validated against transistor level simulations referring to a commercial 28nm FDSOI CMOS process. Different divide-by-8 circuits following different optimization strategies have been designed in the same 28nm CMOS technology showing the effectiveness of the proposed methodology

Delay models and design guidelines for MCML gates with resistor or PMOS load

In this paper we present propagation delay models for MCML gates with resistor- or triode-PMOS-based output I–V conversion. The dependence of the parasitic capacitance of triode PMOS devices is accurately evaluated for the first time in the literature. The proposed models are able to accurately predict the propagation delay as a function of the bias current ISS in different design scenarios which require different tradeoffs between speed, area and power efficiency. The proposed models are validated against transistor level simulations referring to a 28 ​nm CMOS process showing a maximum percentage error lower than 6.5%. Based on these models, a comparative analysis is carried out and useful guidelines for the design of MCML gates are proposed

10-GHz fully differential Sallen–Key lowpass biquad filters in 55nm SiGe BICMOS technology

Multi-GHz lowpass filters are key components for many RF applications and are required for the implementation of integrated high-speed analog-to-digital and digital-to-analog converters and optical communication systems. In the last two decades, integrated filters in the Multi-GHz range have been implemented using III-V or SiGe technologies. In all cases in which the size of passive components is a concern, inductorless designs are preferred. Furthermore, due to the recent development of high-speed and high-resolution data converters, highly linear multi-GHz filters are required more and more. Classical open loop topologies are not able to achieve high linearity, and closed loop filters are preferred in all applications where linearity is a key requirement. In this work, we present a fully differential BiCMOS implementation of the classical Sallen Key filter, which is able to operate up to about 10 GHz by exploiting both the bipolar and MOS transistors of a commercial 55-nm BiCMOS technology. The layout of the biquad filter has been implemented, and the results of post-layout simulations are reported. The biquad stage exhibits excellent SFDR (64 dB) and dynamic range (about 50 dB) due to the closed loop operation, and good power efficiency (0.94 pW/Hz/pole) with respect to comparable active inductorless lowpass filters reported in the literature. Moreover, unlike other filters, it exploits the different active devices offered by commercial SiGe BiCMOS technologies. Parametric and Monte Carlo simulations are also included to assess the robustness of the proposed biquad filter against PVT and mismatch variations

An improved reversed miller compensation technique for three-stage CMOS OTAs with double pole-zero cancellation and almost single-pole frequency response

This paper presents an improved reversed nested Miller compensation technique exploiting a single additional feed-forward stage to obtain double pole-zero cancellation and ideally single-pole behavior, in a three-stage Miller amplifier. The approach allows designing a three-stage operational transconductance amplifier (OTA) with one dominant pole and two (ideally) mutually cancelling pole-zero doublets. We demonstrate the robustness of the proposed cancellation technique, showing that it is not significantly influenced by process and temperature variations. The proposed design equations allow setting the unity-gain frequency of the amplifier and the complex poles' resonance frequency and quality factor. We introduce the notion of bandwidth efficiency to quantify the OTA performance with respect to a telescopic cascode OTA for given load capacitance and power consumption constraints and demonstrate analytically that the proposed approach allows a bandwidth efficiency that can ideally approach 100%. A CMOS implementation of the proposed compensation technique is provided, in which a current reuse scheme is used to reduce the total current consumption. The OTA has been designed using a 130-nm CMOS process by STMicroelectronics and achieves a DC gain larger than 120 dB, with almost single-pole frequency response. Monte Carlo simulations have been performed to show the robustness of the proposed approach to process, voltage, and temperature (PVT) variations and mismatches

An ultra-low-voltage class-AB OTA exploiting local CMFB and body-to-gate interface

In this work a novel bulk-driven (BD) ultra-low-voltage (ULV) class-AB operational transconductance amplifier (OTA) which exploits local common mode feedback (LCMFB) strategies to enhance performance and robustness against process, voltage and temperature (PVT) variations has been proposed. The amplifier exploits body-to-gate (B2G) interface to increase the slew rate and attain class-AB behaviour, whereas two pseudo-resistors have been employed to increase the common mode rejection ratio (CMRR). The architecture has been extensively tested through Monte Carlo and PVT simulations, results show that the amplifier is very robust in terms of gain-bandwidth-product (GBW), power consumption and slew rate. A wide comparison against state-of-the-art has pointed out that best small-signal figures of merit are attained and good large-signal performance is guaranteed, also when worst-case slew rate is considered

Design Centering and Yield Optimisation of MMIC’s with Off-Chip Digital Controllers

In this paper, a new methodology to perform yield-oriented design of MMIC’s in III-V technologies is proposed. A digital control of MMIC bias, based on process parameters estimation by on-chip auxiliary circuits, allows yield enhancement. The design centering approach and a distance-dependent correlated statistical model of HEMT devices are used to design the external controller. The design of a MMIC for optical digital systems has highlighted significant yield improvement with respect to previously proposed methodologie

High‐gain, high‐CMRR class AB operational transconductance amplifier based on the flipped voltage follower

A novel class AB operational transconductance amplifier (OTA) topology is proposed, based on a class AB flipped voltage follower. The OTA has class AB behavior, with current boosting both for the load and the compensation capacitors. It has a high gain of (gmr0)4, obtained using a two‐stage structure with cascoded stages, and is a two‐stage Miller‐compensated amplifier employing multipath to remove the positive zero. It has close to rail‐to‐rail output swing (limited by cascoding) and very low common‐mode gain thanks to a replica technique (allowing the use of low‐power common‐mode feedback [CMFB] loops). Ninety‐two decibels of gain and 176 dB of common‐mode rejection ratio (CMRR) without CMFB are achieved using a 40‐nm complementary metal‐oxide semiconductor (CMOS) process. The OTA is used to design a low‐power sample‐and‐hold amplifier (SHA) operating at 5 MSps, a typical application for CMOS OTAs, which has been chosen to verify the proposed circuit's performance and to show that the OTA is robust in Monte Carlo simulations under process variations and mismatches in an actual application

Positive feedback GaAs comparators for SDH/SONET applications

In this paper we present two topologies for differential high-sensitivity comparators, suitable to be implemented in GaAs MESFET/HEMT technologies. Both topologies use positive feedback to compensate for the moderate specific transconductance of GaAs devices, and differ for the implementation of the summation node. The linear and non-linear behaviour of the circuits are analysed, in order to define limitations due to process parametric dispersion using state of art technologies. Circuit simulations are reported to estimate slew rate performance. The topology based on the cascade of two differential cells shows better slew rate performance and results not very sensitive to process parameter dispersion, whereas the topology based on the shunt connection of two differential pairs is more sensitive to process variations but allows to electronically control its DC transfer function